Buffer memories have been used for years for enhancing operation of memory systems. When such a buffer becomes large and is extremely fast, such that the relatively low-performance of a backing store is substantially masked from a using unit, such a buffer has been referred to as a cache. For cost control purposes, it is desired to minimize the size of a buffer memory, particularly when so-called caching characteristics are desired. To date, the contents of a cache are determined by several automatic mechanisms which are usually based upon algorithms of diverse types. A first mechanism is the promotion of data from the backing store to the cache. The purpose of the data promotion is to ensure that the data in the cache is the most likely to be used next by the using unit, such as a central processing unit. With only a data promotion mechanism, the cache would soon fill up, preventing further data from being promoted from the backing store. To ease this problem, replacement algorithms have been designed with mechanisms implementing those algorithms replacing data in the cache with new data being promoted from the backing store. With this combination of data promotion and replacement, the cache is always full of data. Optimizing caching characteristics, i.e., maximizing the so-called device characteristic masking feature of the caching function, requires a relatively large cache. Further, the replacement algorithm may require that data be transferred from the cache to the backing store before new data can be promoted. This action results in a performance degradation. Accordingly, it is desired to provide a caching or buffering function which tends to maximize the caching characteristics with a smaller cache than would be required with the usual data promotion and replacement control mechanisms. Some prior cache mechanisms are next described.
U.S. Pat. No. 4,048,625 shows a first-in, first-out (FIFO) buffer which invalidates data areas upon readout. Data validation in the buffer occurs independently of error conditions. Also, invalidation occurs irrespective of whether data was modified while it was in the buffer.
Lang et al., U.S. Pat. No. 3,845,474 shows invalidating cache data when a first processor reads it when the data is in a so-called "communication table". That is, data accessible by another processor which can change such data independent of the cache-running processor is invalidated.
Chang et al., U.S. Pat. No. 4,197,580 shows a cache having a validity bit for each cache area; upon readout, the validity bit may be reset, i.e., data becomes invalid.
In general, a dual-copy philosphy is used in many cache-backing store situations. That is, a main memory will have one copy, and the cache will have a second copy. Generally, in a processor cache, the data is usually not destroyed as it is read except as set forth in Lang, et al. above.